ATLAS Upgrades For Super LHC

Measuring ABCn ASICs
When the ABCn chips return from fabrication, it will be desirable to test a few thousand die prior to mounting them in the various detector modules being designed by LBL, Rutherford and KEK. We have proposed to the community the use of our semi-automated integrated circuit test equipment used for production testing the ATLAS TRT analog and digital circuits to perform basic digital functionality tests on the ABCn die. We will need to obtain a probe card customized for the ABCn and some interface equipment to attach our probe station to the IC tester and will need to import the verilog test bench files from CERN. A student will begin work on this in the summer so that we will be ready to test when the wafers are returned from fabrication.

The next generation of the ABC chips
The ultimate goal of the silicon strip detector electronics is to achieve the optimal tradeoff between signal quality, high rate operation, and low power while maintaining an architecture that is robust against local failures. To do this, designers will need to migrate to lower power technologies, draw on experience from the ABCn, and consider carefully the power consumption of the entire design. In addition, at the detector level, it will be necessary to solve the power distribution problem in an elegant and sturdy fashion. We hope to contribute on all of these fronts.

Silicon strip readout chips in 0.13 μm processes
After examination of several candidate technologies offered by European and US companies, the CERN microelectronics group has chosen to renew their frame contract with IBM and recommended IBM’s 0.13 μm CMOS technology as offering the best tradeoffs in radiation tolerance, analog performance, power and digital functionality. The SCT community, with CERN leading the chip development, has targeted this technology for their final front end ASIC. Santa Cruz is examining the Silicon Germanium 0.13 μm process to take advantage of its potential for lower power in the analog front end. The Module Controller will be the first major design in 0.13 μm CMOS. We expect to participate in and lead the conceptual development of the overall functionality and to work with other institutions such as TRIUMF to implement a dedicated command decoder capable of directing commands and data between the module and the stave controller. We will also take responsibility for the major analog I/O blocks (the AC coupled LVDS receiver and the programmable current differential driver) as
well as clock generation functions such as the PLL and the DLL. These are areas where we have previous design experience with the TRT and more recent work on upgrade electronics. We expect this work to begin in the summer or fall of 2008 and continue through 2009.