- ...length
- With the present design, which includes four
FPGA devices on each FEC, the total number of bits in the bitstream is 129123
bits. Don't quote me on this number.
- ...signal
- The
signal has a maximum low time
of 5 
, which is determined by internal FPGA circuitry.
- ...programmed
- There is no assurance that the bit stream that has been
loaded into the FPGA is the correct bit stream, or even in the correct format,
beyond the format of the preamble and the internal format of the data frames.
Once the preamble has been accepted, the incoming data stream is scanned for
bits in the pattern of the data frame. It is clear that any random number of
bits of sufficient length could satisfy this criteria and therefore program
the FPGA. However, this would take much longer than the usual programming
time; hence, this time difference might give a handle on determining if the
bit stream is massively corrupt.