Discrete Registers

General Control and Status Register
READ/WRITE
Address = BASE
Auto-clears on power-up

SOFT_RESET-HIGH resets entire board
FIFO_RESET-HIGH resets FIFO address counter to zero
SEQ_RESET-HIGH resets Sequencer to initial state
CMOS_RESET-HIGH resets all CMOS chips
TESTMODE1-when LOW, Sequencer Input CSR shows status of sequencer inputs. When HIGH, Sequencer Input CSR allows software over-ride of sequencer inputs
TESTMODE2-when LOW, Sequencer Output CSR shows status of sequencer outputs. When HIGH, Sequencer Output CSR allows software over-ride of sequencer outputs. (See Sequencer Input and Output CSR below)
TESTMODE3-when HIGH, allows CMOS chip address lines to be driven directly from the CMOS ADDRESS LINE REG (See below)
TESTMODE4-when HIGH, allows direct read and write access to the DRAM, bypassing the FIFO controller. It also holds off the Sequencer from accessing the memory as an (unfortunate) side effect.
SPARE1
SPARE2
CAL_DAC_ENA-When HIGH, enables Calibration DAC to drive the OUT[0], OUT[1], OUT[2] and OUT[3] lines so that respective ADCs can be calibrated. Setting this bit disables all CMOS Chip Selects to avoid the possibility of the CMOS chips interfering with the calibration. Note that this bit must be set before the data value can be written to the CALIBRATION DAC REGISTER, and must be reset before normal operation of the board can be resumed.
Bits 11-15:
CRATE_ADD-Loaded with crate address at start-up time.

CGT24ERR[1]-CGT24 error reset (READ/WRITE)
CGT24ERR[2]-Flags error when rollover occurs out of step with synclr (READ)
CGT24ERR[3]-Flags error when rollover occurs out of step with synclr24 (READ)

ADC value register
READ
Address = BASE

Bits 11-0:
ADCQLX_DATA, 12 bit number returned by most recent ADC conversion of the low gain, short OR long integrate (see LGISEL) signal (OUT[0]). Or, ADCQHL_DATA12 bit number returned by most recent ADC conversion of high gain, long int. sig. (OUT[2]).
Bits 27-16:
ADCQHS_DATA, 12 bit number returned by most recent ADC conversion of the high gain, short int. sig. (OUT[1]). Or, ADCTAC_DATA, 12 bit number returned by most recent ADC conversion of the TAC (OUT[3]).

Voltage monitoring ADC control/status register
READ/WRITE
Address = BASE

Bits 11-0:
Number returned by last voltage monitor ADC conversion (read only)
Bit 12:
BUSY*-LOW indicates ADC was busy during read, data invalid (read only)
Bits 17-13:
Number of channel to monitor (write) or channel number selected (read)
00000:
-3.3 (supply)
00001:
-2.0 (reference)
00010:
-1.0 (reference)
00011:
1.0 (reference)
00100:
3.3 (supply)
00101:
4.0 (reference)
00110:
4.0 (supply)
00111:
5.0 (reference, divided by 5)
01000:
-8.0 (supply, divided by 5)
01001:
8.0 (supply, divided by 5)
01010:
-15.0 (supply, divided by 5)
01011:
15.0 (supply, divided by 5)
01100:
-24.0 (supply, divided by 5)
01101:
24.0 (supply, divided by 5)
01110:
-5.2 (supply, divided by 5)
01111:
5.0 (supply, divided by 5)
10000:
unused
10001:
unused
10010:
unused
10011:
unused
10100:
high voltage current monitor
10101:
calibration DAC output
10110:
0.8 (reference)
10111:
temperature monitor (conversion factor = ?)

Pedestal enable register
make READ too!/WRITE
Address = BASE

Bits 31-0:
PEN32-1-HIGH enables pedestal for channel 32-1.

DAC programming input register
READ/WRITE
Address = BASE
(See Sec. 4.2 on page for programming information.)

DACCLK (WRITE)-clocks in data to DACs
DACSEL (WRITE)-selects DACs (all DACs are selected simultaneously)
Bits 18-2:
DACDIN[17-1] (WRITE)-DIN lines for 17 octal DAC chips
Bit 2:
RMPC2 (channels 1-4, 5-8,,29-32)
Bit 3:
VLI (channels 1-4, 5-8,,29-32)
Bit 4:
VSI (channels 1-4, 5-8,,29-32)
Bits 5-8:
VTH (channels 1,,32
Bits 9-16:
VBAL (channels 1,1,,32,32)
Bit 17:
RMPC1 (channels 1-4, 5-8,,29-32)
Bit 18:
ISETA1, ISETA0, ISETM1, ISETM0, TACREF, VMAX, VRES (OUT0-6 of DAC)
Bits 18-2:
DACDOUT[17-1] (READ)-DOUT lines for 17 octal DAC chips

Calibration DAC register
make READ too!/WRITE
Address = BASE
Auto-clears on power-up and master reset

Bits 11-0:
12 bit value written to calibration DAC

OUT[0] enable-HIGH switches the DAC output onto the OUT[0] line
OUT[1] enable-HIGH switches the DAC output onto the OUT[1] line
OUT[2] enable-HIGH switches the DAC output onto the OUT[2] line
OUT[3] enable-HIGH switches the DAC output onto the OUT[3] line

High voltage card control/status register
READ/WRITE
Address = BASE
(See Sec. 4.3 on page for programming information.)

HVDATACLK (WRITE)-Clock for shifting data into and out of HVC
HVDATAIN (WRITE)-Data to be clocked INTO the HVC
HVLOAD (WRITE)-Enables various control functions (hvtst,tstenbl,etc.)
HVDATAOUT (READ)-Data to be clocked OUT OF the HVC

CMOS spy-on-data-output register
READ
Address = BASE

Bits 30-0:
CMOS internal registers
Bit 31:
CREG_ERROR-HIGH indicates that the FEC was busy during read attempt: Data is invalid.

CMOS full register
READ
Address = BASE

Bits 31-0:
FULL32-1-HIGH indicates CMOS #32-1 is full so subsequent events cannot be processed

CMOS chip select register
READ
Address = BASE

Bits 31-0:
CHIP_SELECT*32-1-LOW indicates CMOS #32-1 has been selected

CMOS programming (SERDAT) register A
READ/WRITE
Address = BASE
(See Ref. [1] for information on how to program the CMOS chips.)

SHFTCLKT-Clock for shifting data into bottom CMOS#16-1
SERSTORT-Serial data STORE signal for bottom CMOS#16-1
Bits 17-2:
DATIN-Data to be clocked into bottom CMOS#16-1

CMOS programming (SERDAT) register B
READ/WRITE
Address = BASE

SHFTCLKT-Clock for shifting data into top CMOS#32-17
SERSTORT-Serial data STORE signal for top CMOS#32-17
Bits 17-2:
DATIN-Data to be clocked into top CMOS#32-17

CMOS set LGISEL register
READ/WRITE
Address = BASE

LGISEL-Low gain integrate select: when low, allows the low gain charge input to be integrated for short integrate; when high, long integrate. One line for all 32 channels.

Board ID register
READ/WRITE
Address = BASE
(See Sec. 4.4 on page for programming information.)

SK-clock data in or out of ID chips
Bits 6-1:
CS-select one of the 6 ID chips

000001:
Mother board
000010:
Daughter board #1
000100:
Daughter board #2
001000:
Daughter board #3
010000:
Daughter board #4
100000:
High voltage card

DI-line containing the input data for the selected ID chip
PRE-programming pin, normally set ???
PE-programming pin, normally set ???
DO-line containing the output data from the selected ID chip