Sequencer Registers

Sequencer input control/status register
READ
ADDRESS = BASE
(Note: this register is READONLY during normal operation, but WRITE in certain test modes.)

CREG_REQ-HIGH indicates VME interface is requesting access to the CMOS registers
MEMACK2*-LOW indicates that the Dual-Port Controller has acknowledged a request from the sequencer to store front end data in the DRAM fifo
Bits 6-3:
TAG0-4-binary encode of chip select.

Sequencer output control/status register
READ
ADDRESS = BASE

FECBUSY-indicates that the Sequencer is busy processing front end data
RD_STROBE-State of READ STROBE line to CMOS chips
LATCH1-HIGH-going edge indicates to latch first byte of digital data out of the CMOS chip
LATCH2-HIGH-going edge indicates to latch second byte of digital data out of the CMOS chip
LATCH3-HIGH-going edge indicates to latch third byte of digital data out of the CMOS chip
LATCH4-HIGH-going edge indicates to latch fourth byte of digital data out of the CMOS chip
FECSEL-HIGH indicates front end data has been selected for processing
CREGSEL-HIGH indicates a VME CMOS register request has been selected for processing
CONV_DONE-HIGH indicates ADC conversion is done
ADC_CONVERTstar-LOW indicates to start ADC conversion
CAD_EN-HIGH indicates that CMOS addresses have been enabled
MEMREQ2*-LOW indicates that a request has been made from the Sequencer to the Dual-port memory controller to write data to DRAM
ENW1*-LOW indicates that the first digital longword, containing cmos data (trigger ID, cell address, error status, crate/channel ID) has been enabled onto the local DRAM data bus
ENW2*-LOW indicates that the second digital longword, containing QHS and QLX, has been enabled onto the local DRAM data bus
ENW3*-LOW indicates that the first third digital longword, containing TAC and QHL, has been enabled onto the local DRAM data bus
CHOLD-Holdoff signal that prevents invalid readout of Sequencer internal registers.

CMOS data available (DAVAIL) register
READ (WRITE in TESTMODEs only)
ADDRESS = BASE

Bits 31-0:
DAVAIL32-1-HIGH indicates CMOS chip #32-1 has data to be processed

CMOS chip select (CSEL) register (usable in TESTMODE1,2 only)
READ/WRITE
ADDRESS = BASE

Bits 31-0:
CSEL31-0-HIGH indicates CMOS chip #32-1 is selected

CMOS chip disable register
make READ too!/WRITE
ADDRESS = BASE
Auto-clears on power-on-reset

Bits 31-0:
CHIP_DISABLE31-0-HIGH disables CMOS chip #32-1

CMOS data output register
READ
ADDRESS = BASE

Bits 7-0:
shows the 1st byte output from the CMOS chip last accessed by the sequencer
Bits 15-8:
shows the 2nd byte output from the CMOS chip last accessed by the sequencer
Bits 23-16:
shows the 3rd byte output from the CMOS chip last accessed by the sequencer
Bits 30-24:
shows the 4th byte output from the CMOS chip last accessed by the sequencer
Bit 31:
Error bit, shows error status of last CMOS data transfer word (used primarily for internal CMOS data register reads)

FIFO write pointer register
READ
ADDRESS = BASE
Clears on power-on-reset, master_resetand fifo_reset

Bits 19-0:
A 20-bit number that indicates the address of the write pointer in the 4Mbyte address space of the online memory

FIFO read pointer register
READ
ADDRESS = BASE
Clears on power-on-reset, master_resetand fifo_reset

Bits 19-0:
A 20-bit number that indicates the address of the read pointer in the 4Mbyte address space of the online memory

FIFO pointer difference register
READ
ADDRESS = BASE
Clears on power-on-reset, master_resetand fifo_reset

Bits 19-0:
A 20-bit number that indicates the difference between the address of the read and write pointers in the 4Mbyte address space of the online memory