The DACs

There are 17 octal DACs which provide us with the capability of programming up to 136 references voltages. Seven of these DACs are MAXIM 529s and ten are MAXIM 528s (the 528 can operate with a wider range of reference voltages than the 529). Each device accepts two sets of reference voltages, each of which can control 4 of the 8 internal DACs on a chip. The output voltages are given by

Both devices are programmed in the same manner, as described in the MAXIM 1993 New Releases Data Book:

The MAX528/529 are programmed by 16 data bits in two 8-bit bytes, the address pointer bits (A7-A0) followed by the data byte (D7-D0). These bits enter a shift register serially throught DIN: A7 first, and D0 last. The data exits DOUT 16 clock cycles later in the same order.

Data at DIN is shifted into the first register (while all 16 register bits shift forward one stage) on a rising DACCLK edge, while holding DACSEL high. This must occur 16 times to load all data bits into the shift registers. On the rising edge of DACSEL, data in the 16 shift registers is transferred as addressed and DACCLK is disabled.

There are three types of instructions: NOP, SET DAC, and set buffer modes.

• No operation (NOP) is implemented when all 8 address pointer bits (A7-A0) and data bit D7 are 0. Data in D6-D0 is ignored. When this instruction is clocked in, no registers are updated and the outputs remina unchanged. NOP is a place saver when multiple chips are daisy-chained.
• SET DAC is implemented when at least one of the 8 address pointer bits (A7-A0) is logic 1. SET DAC updates the digital code of any or all DAC registers (and their corresponding DAC outputs) to a single new value. The new value is contained in the data byte (D7-D0). Each address pointer bit (A7-A0) selects a DAC output. Any combination of outputs can be updated simultaneously with one 16-bit instruction. Remember that address 0000 0000 is reserved for NOP and set buffer modes. SET DAC does not change the buffer modes.
• Set buffer modes is implemented when all 8 address pointer bits (A7-A0) are logic 0 and data bit D7 is 1. Data in D6 is ignored. When this instruction is issued, data bits D5-D0 are transferred to the mode registers only; the DAC registers are unchanged.

  Enabling and disabling the 8 buffers is done in 4 pairs by data bits D1, D2, D4 and D5. D1 controls bufferes 6 and 7, D2 4 and 5, D4 2 and 3, and D5 0 and 1. A logic 1 enables a buffer pair (full- or half-buffered mode); a logic 0 disables a buffer pair (unbuffered mode).

  Full-buffered and half-buffered modes are set by two data bits, D0 and D3. D0=1 enables full-buffered mode for OUT4-7, D3=1 enables full-buffered mode for OUT0-3. D0=0 or D3=0 enables the respective half-buffered modes.

As indicated in the description of the DAC programming input register, a 19-bit word is used to program the DACs. Bit 0 of this word is DACCLK, bit 1 DACSEL, and the remaining 17 bits are the DIN signals for each of the 17 DACs. To clock 1 bit of data into each of the 17 chips in this manner requires two write cycles. This is the case because we must insure that the data on the upper 17 bits is valid when DACCLK goes high. The proper sequence is therefore:

This scheme clearly wastes a clock cycle relative to the most efficient scheme you could imagine. However, it was found that such a scheme substantially simplified the hardware, and since DAC programming happens relatively infrequently, the time lost is not consequential.