In order for an FPGA to carry out a set of instructions, it must first be
programmed. The program consists of a bit stream, that is roughly bits in length
. The bit stream itself consists of a
40 bit preamble containing information about the total length of the bit
stream and the number of devices in the daisy chain, if applicable. The rest
of the bit stream is divided into frames, whose beginning is marked by a 0 and
whose end is marked by three 1's. The end of the bit stream is marked by a
postamble, which is a number of 1's, where the number of 1's is at least four.
On power-up, the FPGA does some internal initialization of its circuitry which
lasts up to . The end of this sequence is indicated by the release of
the
pin, but it can be delayed by asserting
until the external processor is ready to start
configuration. The present design of the FEC32 takes advantage of this
feature to delay the configuration by asserting
to save on
backplane resources. At the end of the power-up sequence, the FPGA determines
how it is going to be programmed by sampling the inputs on its three
configuration pins. On the FEC32, these input pins will be held to the SLAVE
SERIAL MODE settings. This tells the chip to expect to be programmed via an
external microprocessor, which will supply the input data stream and the
sampling clock. The FPGA will, in return, supply a
signal to show that it has been successfully programmed after having received
its entire bit stream. The data is clocked into the FPGA on the rising edge
of the
clock signal
. Internally,
the FPGA waits until it is programmed. Once this condition is met, the
outputs of the FPGA become active, and the chip asserts the
signal to indicate that it has been successfully
programmed
.
If the FPGA is the first in a series of chips being loaded in a daisy-chain
fashion, as will be the case in the FEC32, the story is a bit different. The
preamble is sent through all chips at the same time, offset by half a clock
cycle. However, the first chip in the chain is programmed first in the Xilinx
methodology of daisy chaining. The serial output of the first chip is quiet
after having passed along the preamble until it has read all the bits it needs
to program itself, at which point it starts passing everything along to the
next chip in the chain. It will continue to do so until its internal counter
indicates that it has passed as many bits through as were indicated in the
preamble length count. At this point, the chip will assert its
signal. Hence, in Xilinx FPGA loading, the daisy
chain works in such a way that the first chip in the chain is loaded first, unlike in most other daisy chains.
Reprogramming is achieved by virtually the same steps. Reprogramming is
initiated by asserting the signal and the
signal at the same time. The rest of the process is the
same as the power-up programming sequence.
On the FEC32, programming will occur via a register on the translator card.
It will be possible to program all 17 cards in a crate in parallel, via a
broadcast mode, or one card individually. However, due to the daisy chaining
of the bit stream, it will always be necessary to program all chips when one is
being reprogrammed. A conservative time estimate puts the time spent on
programming all FPGAs on a given FEC at roughly .