Reading the ID Register

The NM93CS06 Serial EEPROM device is divided into 16 16-bit registers. A specific register can be protected against data revision by programming the Protect Register with the address of the first register to be protected against. All of the registers greater than or equal to this selected address are then protected from subsequent modification. This address can be locked into the device, making any future attempt to change the previously entered data impossible.

There 10 instructions which act on the memory of the device, 5 of which function on the EEPROM memory, and 5 which function on the Protect Register. These instructions are READ, WRITE, WRITE ALL, WRITE ENABLE, and WRITE DISABLE for the EEPROM, and PRREAD, PRWRITE, PRENABLE, PRCLEAR, and PRDISABLE for the Protect Register. All Data-In signals are clocked into the device on the low-to-high SK (Serial Data Clock). If the Protect Register Enable (PRE) pin is not held high, all instructions will be exercised on the EEPROM memory instead of the Protect Register.

Once the Protect Register has been programmed and protected against, it may be read from by making use of the Protect Register Read (PRREAD) instruction. This command outputs the address reserved in the Protect Register on the Serial Data Output (DO) pin. The 8-bit address stored in the memory protect register is transferred to the serial out shift register once the PRREAD instruction has been executed. A dummy bit (logical 0) precedes the 8-bit address string. In short, the PRREAD function reads the address stored in the Protect Register.

The EEPROM memory may be read from executing the READ (Read and Sequential Register Read) instruction. This instruction outputs serial data on the DO pin. After the READ command has been received the instruction and address are decoded and then data is transferred from a selected memory register into a 16-bit serial-out shift register. As with PRREAD, a logical 0 dummy bit precedes the 16-bit data output string. A low to high transition of the SK clock initiates output data changes. In the Sequential Register Read mode, the memory automatically cycles to the next register after each 16 bits of data are clocked out. The dummy-bit is suppressed in this mode of operation so that a continuous string of data may be read out.

More prosaically, data stored in the chip's memory at a specified address is read out by following these steps:

1. set appropriate CS high to select a chip
2. set PRE low
3. start SK (clock); sensitive to lowhigh transitions
4. clock in the bit pattern 110xxAAAA into DI, left-most bits first, where x = (don't care) and A is the address of the particular register to read
5. when the last Address bit is clocked in, the DO line will issue a dummy bit at logical 0, followed by the D15-D0, the data in the register
6. if SK continues run, subsequent registers will be clocked out onto the DO line, without any dummy bits present