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Clock

Register 4 is a single 16 bit read/write register arranged in three groups of four bits for the three different clocks required by the FEC - Memory, Sequencer, and ADC. In each group the first bit is used to clock in frequency set data to the respective frequency synthesizer, the second bit is the data to be clocked in, the third bit is the enable for the synthesizer output and the fourth bit is ored in with the synthesizer output to be used as a software driven clock. Bits 12 - 14 are spares. Bit 15 is an overall clock enable for all of the clocks. The system comes up reset to a disabled state and requires active intervention by the master to set the frequencies and turn on the individual clocks.


cowen@upenn5.hep.upenn.edu
Thu Dec 28 10:28:51 EST 1995