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The Translator Card

The Translator Card in the original configuration was required only to convert from standard VME 5V signals over 96 pin DIN 41612 connectors to lower voltage signals (GTL and ECL 0.8V swing) over 165 pin Futurebus style connectors - largely to avoid possible electrical interference with sensitive PMT signals with the lower voltage swings and greatly increased number of ground connections. The Translator card also served to do some of the high level address decoding from 31 bit VME addresses (A<31..1>) to the more restricted address space actually needed for the SNO FECs - 20 bits to describe the 1MW (4MB) FEC memory and 4 bits to name a particular FEC within a crate.

By splitting the original Translator Card into two physical objects - XL1 and XL2 - which are joined by a cable, it is possible to accomplish the above tasks and, in addition, obtain greater isolation from electrical pickup, greatly increase the crate to crate bandwidth, and somewhat reduce the costs. In addition, other insights have allowed us to increase the functionality and decrease the complexity of the planned system. The interconnection cables between the two halves of the translator are shown in Figure 4.



cowen@upenn5.hep.upenn.edu
Thu Dec 28 10:28:51 EST 1995