The astute observer will wonder, at this point, what happened to
bits A<15..11> from the VME bus - since the short register
space (AM=29) comprises a full 16 bit area. For SNObus these five bits
are used to select a particular crate out of the 30 possible
(all ones and all zeros are not legal crate names) crates. Similarly
for memory space (AM=09), five bits are also reserved for crate
address, but in this case there is a choice of any five bits in
the ten bit range A<31..22>. For the preliminary design
we have chosen to use A<26..22> for the crate address and
require that A<31..27> be identically zero. However, any
combination of five bits in the range may be used for crate addressing
and any combination of the five remaining bits may be required for
a valid SNObus regime - this decoding is done in an FPGA and can
be changed relatively easily. The XL1 card automatically uses
either A<15..11> or A<26..22> to compare with the
available crate addresses depending upon whether
the transfer of the moment is AM=29 or 09. This selection of
Register Space or Memory Space that is decoded from the AM lines
is reflected in the Translator internal signal MEMREG (=0
Register Space, =1
Memory Space).
Crate identification is made by matching the proper crate address bits (A<15..11> or A<26..22>) with the hardwired (jumpered) crate geographic addresses from the backplane of each crate. Each XL1 has four simultaneous comparators that examine the five bit Crate Address lines coming from the installed crates and compare those numbers to the VME address bits. Matches, coupled with acceptable Longword, DS0, DS1, and AM states result in a Strobe signal (called Gated Strobe in the schematics) to the correct crate. This strobe signal, coupled with the bits entered in the Select Register, provides the individual Select line to each Front End Card.