As noted above, the individual FEC is represented by a bit in
the Select Register and and by a bit in the Data Available Register.
In the normal course of events
one and only
one bit in the Select Register is true - this is the board that the
DAQ program is presently interrogating or expects to interrogate soon
or, possibly, just the most recent board looked at. However, as any
board with data ready to send to the DAQ will
set its bit in the Data Available register there may be any number of
bits set - from none to 18 (16 FEC + 1 Trigger (were it ever to have any
data) + 1 Translator). Bit 31 of the Data Available register is an
or of the bottom 18 bits so that a simple test for negative number
can determine if there is any data in a given crate. The Select,
Data Available, and
Data Available Mask
Registers are arranged as follows:
Select and Data Available Mask are Read/Write registers while Data Available is Read Only (the actual Data Available bits come directly from each FEC over dedicated point to point backplane lines.
For a normal data transfer, the sequence of operations would be roughly as shown in Figure 5. The bus master could poll an entire crate by reading that crate's Data Available Register and looking for a negative number. Only if the or were true would the master decode the one or more set Data Available bits and then select the board (or, in sequence, the boards) with Data Available set for reading. As shown in detail in the FEC register description note, the master can determine the number of available words of data by one additional read followed by multiple reads of the memory to clear the Data Available condition.
