Main Busses

The data signals carried as busses on the backplane are:

• Data - D<31..0> - 32 single ended read/write bits - GTL
• Address - A<21..2> - 20 single ended write only bits - GTL
• Control - 3 single ended write only bits - GTL
  • Write - equivalent to VME write
  • RegSpace - high for Register addressing mode, low for memory
  • Sysreset - equivalent to VME sysreset
• Control - 1 single ended read only bit - ECL
  • DTACK - equivalent to VME DTACK
• Clocks - Memory, Sequencer, and ADC clocks - differential ECL
• Xilinx Load - 2 single ended write only - CMOS
  • Xilinx Load Clock
  • Xilinx Data In
• Xilinx Done-Prog - single ended read/write - CMOS