Each FEC and the Translator card must also know either its card or crate address in an absolute fashion. Rather than relying on DIP switches or other card based schemes, we have chosen to put hardwired connections on the backplane for this purpose. The FEC addresses are hard encoded to 0V or +5V via four dedicated pins on J2. This address is then picked up by the sequencer during a digitization and included in the data packets. The crate address is set by a jumper field (five bits) at the Translator J2 connector. Each crate must be set up once by installing jumpers for address zeros. This crate address appears as a field in the Translator CSR - Register 2 - it must be read by the DAQ master at startup and then explicitly loaded into each FEC Crate Address Register (see FEC Register List for details). The Crate Address is not included on the backplane because of the number of additional lines required.