- DTMROC - Digital Time Measurment ReadOut Chip

The DTMROC is the digital front end chip for the ATLAS TRT detector. Its purpose is to receive ternary digital signals from the ASDBLR analog front end chip, perform a 3.125ns transient digitization of the low threshold part of the signal and store the digitization for the duration of the level 1 accept latency. On level 1 accept, three successive 25ns periods are serialized and sent off chip.

The chip also contains four, eight bit DACs for controlling the low and high tresholds of two ASDBLR chips. It also has a variable amplitude, variable delay test pulse generator for the ASDBLR chip. It is possible to separately select odd and even channels of the ASDBLR.

There are two versions of the DTMROC in the DMILL technology. The first version was submitted to TEMIC in August of 1999 and wafers were received in December of 1999. The DTMROC99 is a successful design with a few minor caveats.

The DTMROC99 design was modified to fix the known problems and to remove test structures where they negatively affected the performance of the chip.

The as-built specification for the DTMROC99 design is here in PDF format.

Information on threshold DAC matching for the DTMROC99 chip is here .

DTMROC00 reticle and wafermap

  • Wafer Map
  • reticle

    **** Packaging and Hookup ***


    Active signals go to the two outer rows of the FBGA ball locations.
  • DTMROC 2000 FBGA package substrate design.
  • DTMROC 2000 FBGA package Bonding Diagram.
  • DTMROC 2000 FBGA DTMROC die Orientation.
  • DTMROC 2000 FBGA Ball_Grid Orientation.
  • DTMROC 2000 FBGA netlist ( signal to package balls)

  • Bonding diagram for the DTMROC2000 TQFP chip in ps format OR in .jpg format.

    The only difference between DMILL DTMROC1999 and DTMROC2000 is that hard_reset_hi was removed and replaced with spare1 and spare2. The two packaged chips are pin-for-pin replaceable except for spare1 and spare2. We have renamed:

    spare1 --> Shaper_select

    spare2 --> spare

    Review Material Here Jan 2003

    DSM version (Submitted January 2002 - Received March 12, 2002)

    A collaborative design effort by The CERN microelectronics group and the Penn Instrumentation group. The DTMROC was ported into a 0.25um CMOS process in January 2002. Functionality has been added to monitor the on chip supply voltage and temperature. An off chip monitoring function is added as well. While similar in function, the DSM DTMROC is not fully compatible with the previous versions.
  • DSM DTMROC SPECIFICATION { Work In Progress } PDF OR DOC file. The "Word" version allows indexed jumps to references from the Table of contents and from outline references within the text.

    Custom DSM Analog Blocks

  • Power Up Reset
  • Ternary Receiver Low level Differential Current Receivers to decode Three Level ASDBLR trigger outputs.
  • LVDS Driver Data Out Driver
  • LVDS driver for CMD_OUT with "Wire OR" mode.
  • Wire Or Circuit for Fast Trigger outputs CMD out has been revised to allow a fast trigger output of the Logical 'OR' of all unmasked Ternary inputs. A oneshot on each channel guarantees a minimum output witdth of > 10ns.
  • Voltage and Temp Sense Block A rudimentary on chip monitoring system is implemented using 2 additional D/A blocks in conjunction with a comparator to set register bits.
  • Comparator for Voltage/Temp/External input Sensing See Voltage and Temp Sense Block writeup for simulation results.
  • Dual 8 Bit D/A BLOCK 4 Dual D/A blocks are used in the DTMROC to provide a total of four ASDBLR thresholds and two monitor reference voltages and two Test Pulse Output References. D/A designed by Cern Micro Electronics is implemented as a Dual D/A block for the DTMROC Final Layout and simulations done at Penn.
  • Xenon Test Pulse Output Two Programmable Delay and Programmable Amplitude Test Pulse outputs that mimic the TRT Straw tube signal are provided.

    Fabricated ASIC Wafer Info

  • 8" DSM DTMROC wafer
  • DSM DTMROC Labeled Pad Frame
  • Bonding Diag into TQFP pkg
  • Wafer Serializing map

    NEW Oct 2002 FBGA Package for DSM-DTMROC

  • DSM-DTMROC FBGA design
  • DSM DTMROC FBGA bonding diagram
  • DTMROC-S Signal/die pad/FBGA ball cross reference
  • DTMROC-S Physical Ball/Signal Map

    MEASUREMENTS of Double Pulse Resolution - Using two Lecroy 9211 pulsers with attenuators and a charge injector designed to simulate the Straw signal ( designed by Anatoli Romaniouk (CERN)) we inject dual pulses into one channel of the ASDBLR01 on the TB4 test board. This board is stuffed with a DSM DTMROC and we examine the effects of capacitance on the Ternary Inputs to the DTMROC. The ASDBLR Ternary drive current is 440uA total. Since the ASDBLR inputs are unchanged during test runs any differences in population of the 24, 3.1ns time bins can be attributed primarily to the effects of capacitive loading of the Ternary Receiver inputs. Tests use 0 and 15pF of added capacitance to the ternary inputs.

  • Two 4fC pulses with a 2.5fC threshold Time separation of 15 through 20ns. The delay of both pulses is shifted by 2.2ns in the 15pF added case to align the time bin amplitudes. No other adjustments are made.
  • 25fC pulse followed by 4.5fC pulse 26ns separation examines effects of Ternary High level input
  • 25fC pulse followed by second pulse (~4.5fC) Delay between pulses 26ns. The delay due to the added input capacitance is clearly visible. The amplitude of the 0pF added capacitance case is reduced (4.5--> 4.2pF) keep the population of the time bins similar. case.

    Driving Ternary Inputs from 3.5V Digital Logic

  • Text Description
  • Schematic
    Paul T. Keener
    Last modified:Nov 14, 2003 FMN