The picture below shows the set-up used for the measurements:
a "3 stack" front-end board plugged into a passive rigid board, with
a protection input board attached at the input.
For calibration purposes, a pulse step injector designed by Mitch was
used (also shown in the picture). For any channel, the addition of
the protection input
board plus the step injector will typically result in an
input capacitance of approximately 10 pF. The protection input board, as
well as the step pulse injector and the ground pins of the passive
board, are grounded to the
common reference of one aluminum plate in the laboratory table
(shown in the figure) by means of copper tape. No other shielding is
provided.
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The step pulse injector allows to calibrate each channel separately.
Charge is injected sending three different pulses, corresponding to
2.0, 3.1 and 4.2 fC, respectively. The step pulser was calibrated
using a Lecroy oscilloscope.
For each value of the injected charge, a threshold scan is run, and
the 50% efficiency point is measured (a hit is defined as the presence
of a level above threshold in any of the 8 time bins of all the
3 bunch crossings). Plotting the 50% point in DAC counts
versus the input charge, we calibrate the DAC in fC (see figures
below) assuming a linear behavior between 1-4 fC of input charge.
Figure 1
Figure 2
Figure 3
These two figures show the gain (in DAC counts/fC) and the offsets
for all the 16 channels (channel 12 is disconnected). In average,
the gain is approximately 330 electrons per DAC count.
Figure 4
Figure 5
To check the relative correctness of the calibration, the following
plots show the aspect of the S-curves for all the channels before (the
first two) and after the calibration (the last one).
Figure 6
Threshold scan for all the channels of the "good" chip.
Figure 7
Threshold scan for all the channels of the "noisy" chip.
Figure 8
Calibrated threshold scan for all channels of both chips.
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The figures below show the noise (RMS) of all channels. The noise
is computed performing a threshold scan (where hits are defined as
in the previous section) and fitting the S-curve to an erfc
function. We recall that one DAC count is approximately 330 electrons.
Note that the noise IS DIFFERENT depending on the input charge. For
most of the channels, at
higher input charge the noise tends to decrease.
This is still not understood, an preliminary we hypothesize
that this feature is a consequence of the clock noise pick-up (see
below).
Figure 9
Figure 10
The two figures below show the 50% efficiency point as a function of
the time bin. For each time bin, we define a hit as the presence
of a level over the threshold in that particular time bin,
and in that manner we build an S-curve
for each time bin. The first plot shows the S-curves
for the channels of one
ASD chip, and the second one for the channels of the other ASD chip.
One of the ASDs is substantially noisier than the other.
This circumstance is still not understood and is believed
due to front-end layout issues.
Figure 11
Figure 12
The figures below show the same situation, but when a pulse with
charge of 2,3 and 4 fC (the legend is wrong) is injected.
Figure 13
Figure 14
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The noise rate at a given threshold is defined as the number of leading
edges (transition from 0 to 1) in any of the 3 bunch crossings,
divided by 75 ns.
The figure below shows the accumulative number of
leading edges in any of the three
bunch crossings over 500 events. Note that in channel 6 a charge of
4 fC is injected.
Figure 15
The two figures below show the noise rate for all the channels
as a function of the threshold for the "quiet" ASD (upper figure)
and for the noisier ASD (lower figure). Taking into account the calibration
described in the previous section, a threshold
of 76 DAC counts corresponds approximately to 2fC.
Figure 16
Figure 17
To investigate the effect of the clock noise (which has a frequency
of 40 MHz), the next two figures show the noise rate for each time bin
(i.e only leading edges taking place in that particular time
bin are taken into account) as a function of the threshold level,
for a good channel and for
a channel with large clock noise pick-up. Taking into account
the calibration
described in the previous section a threshold
of 76 DAC counts corresponds approximately to 2 fC.
Figure 18
Figure 19
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For the near future, this an open list of incoming tasks to be addressed:
(the order of the list attempts to set a certain level of priorities)
- Measurements on the barrel module ("Duke" Module)
- Noise performance, clock noise pick-up and
preliminary grounding/shielding studies
- Calibration of the internal test pulser with respect to
the external pulser (step injector, Anatoli test pulser..)
- Random Timming Noise Distribution
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Antoni MUNAR
Last modified: Thu Feb 23 13:45:34 EST 2023