2003 Summer Test Beam Log
Sun Aug 10 09:47:33 WEST 2003
Current patch pannel connections and mapping.
______________________________
| |
| ROD 1: 0x23000000 TTC: 0xd |
| |
| FE 1: AR1FL |
| |
| FE 0: AR1FS |
|_____________________________|
| ROD 0: 0x24000000 TTC: 0xc |
| |
| FE 1: AR2FS |
| |
| FE 0: broken |
|_____________________________|
AR2FS
The notation in the jumper is wrong. The right one is:
|15 10| |14 9| |13 1|
Currently selected positions 15, 14 and 13
The maping of the positions, masks and address is:
(AR2FS with jumper plugged)
Position | Address | Mask | Rod Chip |
1 | 0x1 | As position 13 | -- |
2 | 0x2 | 0x1 | 12 |
3 | 0x3 | 0x2 | 11 |
4 | 0x4 | 0x4 | 10 |
5 | 0x5 | 0x8 | 9 |
6 | 0x6 | 0x10 | 8 |
7 | 0x7 | 0x20 | 7 |
8 | 0x8 | 0x40 | 6 |
9 | 0x9 | As position 14 | -- |
10 | 0xa | As position 15 | Not working |
11 | 0xb | 0x200 | 3 |
12 | 0xc | 0x400 | 2 |
13 | 0xd | shows in the other group | to confirm |
14 | 0xe | 0x80 | 5 |
15 | 0xf | 0x100 | 4 |
AR1FL
Position | Address | Mask | Rod Chip |
1 | 0x11 | 0x80 | 5 |
2 | 0x12 | 0x8 | 9 |
3 | 0x13 | 0x4 | 10 |
4 | 0x14 | 0x100 | 4 |
5 | 0x15 | 0x40 | 6 |
6 | 0x16 | 0x10 | 8 |
7 | 0x17 | 0x20 | 7 |
8 | 0x18 | 0x2 | 11 |
9 | 0x19 | 0x1 | 12 |
10 | 0x1a | | |
11 | 0x1b | 0x200 | 3 |
AR1FS
Position | Address | Mask | Rod Chip |
1 | 0x1 | 0x100 | 4 |
2 | 0x2 | 0x10 | 8 |
3 | 0x3 | 0x8 | 9 |
4 | 0x4 | 0x200 | 3 |
5 | 0x5 | 0x80 | 5 |
6 | 0x6 | 0x20 | 7 |
7 | 0x7 | 0x40 | 6 |
8 | 0x8 | 0x4 | 10 |
9 | 0x9 | 0x2 | 11 |
10 | 0xa | 0x1 | 12 |
Wed Aug 6 23:28:29 WEST 2003
AR1FS performance. Attached to module. Cooling on. No HV
Below are shown. Thresholds scan for all the chips. Noise rate as a function of the
threshold (120 DAC approx 2 fC). Note: the noise tails for high thresholds are believed to be due
to bad format events that will not show up in the real DAQ. Note also that in the plots address begin from zero.
It should begin from 1 (they are shifted by 1. The position on the board for each address, see the AR1FS info page)
########### DAC threshold for rate below 300 kHz
## CHIP 0 ROD CHIP: 4
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: |100| 97|103|104|107| 96| 98| 95|103| 97| 94| 96|101| 95| 94| 94|
## CHIP 1 ROD CHIP: 8
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 93| 92| 98| 98|100| 90|103| 99|101|101|104|100| 99| 98|105|104|
## CHIP 2 ROD CHIP: 9
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 95| 93| 95| 89| 91| 94| 96| 98| 97| 92| 86| 92| 97| 94| 18| 90|
## CHIP 3 ROD CHIP: 3
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 98| 93|100|101| 98|111|136| 91|152|136| 97|125| 95|150| 91|143|
## CHIP 4 ROD CHIP: 5
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 98| 99| 99| 18|106|106|121| 99|121|112|100|105| 97|102| 91|106|
## CHIP 5 ROD CHIP: 7
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 97| 18| 92| 89| 92| 87| 84| 91| 92| 91| 18| 89| 90| 90| 89| 92|
## CHIP 6 ROD CHIP: 6
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 95| 94| 96| 87| 99| 97| 97| 91| 91| 94| 97| 93| 81| 91| 90| 18|
## CHIP 7 ROD CHIP: 10
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: |106| 18|122|102|117| 18|114| 99| 52|134|109| 96|105| 18|101| 97|
## CHIP 8 ROD CHIP: 11
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: |102| 89| 86|106| 96|112|151| 89| 18|140| 89|133|100|144| 98|154|
## CHIP 9 ROD CHIP: 12
channel: | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15|
-------------------------------------------------------------------------------------
threshold: | 18| 97| 87| 96|122|117|124|110| 99|134| 97|129| 99|106| 94|106|
Mon Aug 4 10:37:46 WEST 2003
Patch Panel connections
______________________________
| |
| ROD 1: 0x24000000 TTC: 0xd |
| |
| FE 1: nothing |
| |
| FE 0: AR2FS |
|_____________________________|
| ROD 0: 0x23000000 TTC: 0xc |
| |
| FE 1: AR1FL |
| |
| FE 0: AR1FS |
|_____________________________|
Sun Aug 3 13:40:02 WEST 2003
AR2FS is going to be in ROD 0, FE 0
The notation in the jumper is wrong. The right one is:
|15 10| |14 9| |13 1|
The maping of the positions, masks and address is:
(AR2FS with jumper plugged)
Position | Address | Mask | Rod Chip |
1 | 0x1 | 0x1 | 12 |
2 | 0x2 | 0x2 | 11 |
3 | 0x3 | 0x4 | 10 |
4 | 0x4 | 0x8 | 9 |
5 | 0x5 | 0x10 | 8 |
6 | 0x6 | 0x20 | 7 |
7 | 0x7 | 0x40 | 6 |
8 | 0x8 | 0x80 | 5 |
9 | 0x9 | 0x100 | 4 |
10 | 0xa | | |
*
11 | 0xb | 0x400 | 2 |
12 | 0xc | 0x800 | 1 |
13 | 0xd | 0x1 | 12 |
14 | 0xe | 0x100 | 4 |
15 | 0xf | 0x200 | 3 |
AR1FL ROD 0 FE 1
Position | Address | Mask | Rod Chip |
1 | 0x11 | 0x80 | 5 |
2 | 0x12 | 0x8 | 9 |
3 | 0x13 | 0x4 | 10 |
4 | 0x14 | 0x100 | 4 |
5 | 0x15 | 0x40 | 6 |
6 | 0x16 | 0x10 | 8 |
7 | 0x17 | 0x20 | 7 |
8 | 0x18 | 0x2 | 11 |
9 | 0x19 | 0x1 | 12 |
10 | 0x1a | | |
11 | 0x1b | 0x200 | 3 |
AR1FS ROD 1 FE 0 TTC 0xd dout=5
Position | Address | Mask | Rod Chip |
1 | 0x1 | 0x100 | 4 |
2 | 0x2 | 0x10 | 8 |
3 | 0x3 | 0x8 | 9 |
4 | 0x4 | 0x200 | 3 |
5 | 0x5 | 0x80 | 5 |
6 | 0x6 | 0x20 | 7 |
7 | 0x7 | 0x40 | 6 |
8 | 0x8 | 0x4 | 10 |
9 | 0x9 | 0x2 | 11 |
10 | 0xa | 0x1 | 12 |
Antoni Munar
Last modified: Wed Aug 13 13:35:55 WEST 2003