Voltage Offsets on Active Roof Boards

Background

Due to limitations in the available power supplies, the analog voltages for the active
roof boards were not very uniform during the mobile DAQ tests in the pit. Vcc (+3) dropped
as low as 2.6V on some boards, with Vee (-3) more or less centered around -3.0 (with a
variation of about +/-100mV from board to board). The gain and relative offset of the
ASDBLR are strongly affected by the supplied values of Vcc and Vee. Normally, Vcc should
be 3.000V and Vee should be -3.000V. When these values are varied about these nominal
values, large changes in the threshold response to both noise and actual signals can be observed.

The following tests were made using the AR2BL board installed on the barrel at phi=26.
The supply voltages were varied and measured at the power connector to the board for
each run. First the simplest cases:

Variation of 50% efficiency threshold for noise and ~3fC test pulse from Vcc, with Vee fixed
at -3V:



Variation of 50% efficiency threshold for noise and ~3fC test pulse from Vee, with Vcc fixed
at +3V:



Now we can see the variation in threshold response when both voltages are varied together:


The coefficients are essentially the same as when each voltage was varied separately, so
the effect from each of the voltages can be treated independently (at least in this region).

Notice that the slope for test pulse is larger in each case than the slope for the noise
case. This is not a fundamental difference between noise and a real signal, but just a
variation in the amplitude of the signal being measured. Look at the response for Vcc and
Vee to various amplitude signals:


The various signal level lines form a plane with voltage, DAC counts, and slope as the
axes. By fitting these lines to the equation of a plane, we can find the slope
associated with any given voltage and DAC count response:



Using this, and the knowledge that the voltages act independantly (at least in this region),
we can find an equation that will correct measured DAC values in noise scans based on the
voltages that were set at the time of the run:

NEW DAC = OLD DAC + (Slope_Vcc x (3.000 - Vcc)) - (Slope_Vee x (3.000 + Vee))

Where the slopes are give by the expressions in the calibration plots:

Slope_Vcc = (-11.58 x Vcc) + (0.40 x DAC) + 34.39
Slope_Vee = (-15.04 x Vee) + (-0.34 x DAC) + -65.04

Results
300kHz Rate Distribution

Here is the raw distribution from the final installation checkout tests, before the voltage
correction is applied:


And here is the same plot with the Voltage correction applied:

Barrel Face Plot (A-side only)

Here again is the plot of the raw values from the final installation checkout tests, before
the voltage correction is applied:


And here is the same plot with the Voltage correction applied: