While the overall functionality of the SNO electronics is largely as imagined in the initial Design Criteria Document, a number of important details have been changed or functions have been added to the system and it is appropriate to review the present (and, hopefully, final) state of the architecture at this time. The major hardware change is the dropping of the in-crate VME bus single board computer (SBC) linked to the central DAQ via ethernet and its replacement with a purpose built high speed translator-link card set residing half in the central DAQ VME crates and half in a SNObus crate. This change greatly increases the data bandwidth (by eliminating ethernet), reduces the possibility of electrical interference from VME boards into SNOboards, and allows a more compact address mapping (all of the SNO FECs can be directly addressed by one VME167 card) at the cost of somewhat increased complexity for the translator function and significantly increased design effort for the translator-link as a whole. Nevertheless, the gains noted above plus greatly increased ability (we believe) to deal with the look-back trigger problem in software rather than hardware indicated a significant positive effect from this design change.
Other design changes noted below, but described in greater detail
in separate documents, include mounting all of the custom asics on
a small high density daughter card, separating out NHit drives
as point to point (rather than bussed) lines on the backplane, going
to fully programmable voltage references and adjustments (i.e. the
number of DACs times the number of bits per DAC is greater than ),
adding FEC level circuitry to keep track of trigger ID counts to
in order to avoid ID overrun errors, making all FEC level
Xilinx chips programmable via the SNObus to allow simple hardware
upgrades via SNOMAN Zebra banks, adding the possibility for dual
HV feeds to one crate - selectable on the backplane, and adding
geographic crate addresses to the FEC geographic addresses.