300kHz Rates from Final Installation Checkout in the Pit

This data was taken over the course of two weeks in October of 2006, as the barrel was
being cabled in the pit. A few very strong correction factors have been applied to
this data to cancel out the effect of the low analog voltages, as well as digital-to-analog
ground plane offsets. A description of the methods and correction factors used can
be found here (voltage) and here (grounds).

These plots show the threshold for each channel that would produce a 300kHz rate of
spontaneous noise hits. The ring of lower noise rates for the inner straw layers
corresponds to the double-joint wires in the first 9 straw layers. Any large board-wise
of stack-wise variations (for instance stack 1, side C) are taken to be indications
not of increased noise, but rather of limitations in the voltage and ground corrections.

This is the average 300kHz rate threshold for each straw position within a stack.

This is a histogram of the noise rates for all channels on the barrel. The 'bump'
on the left hand side of the distribution comes from the double-joint wires.

Here is a comparison of 300kHz rate thresholds between sector test and pit test

Clock Noise from Final Installation Checkout in the Pit

What is being called 'clock noise' in these plots is the maximum minus the minimum
50% occupancy threshold for each time bin within a DTMROC chip. This is generally
taken as an indication of clock pick-up, or evidence of some other synchronous noise.

Dead Channels

Here, dead channels are taken to be channels that are fully dead (either from
mechanical failures noted in the module passports or from electronics/installation
failures). 'Soft' electronics failures (i.e. bad offsets/noise) are not included.
The total number of dead channels that are shown on this plot is 926 for A side and
1050 for C side. These number represent an increase of 61 (A) and 145 (C) channels
since the sector tests were completed in November of 2005, of which 32 (A) and 64 (C)
can be attributed to chips that were broken late in the assembly process.
Disclaimer: it is important to note that only one quarter of the 110 new single
channel failures are known to be dead with a high confidence. The rest will need to be
verified with the 'accumulate mode' test (once the patch panels and backend electronics
are installed), which will probably exclude many of these new failures, as well as
identifying other failures that were not caught with the previous methods.

Here are the plots showing the location of the new potentially dead channels that have
arisen since the completion of sector testing: